The Veloce®Coloranimal up Spirit Walking Running Flats Soft Comfortable Lace Women's Corgis Sneakers Casual Team r7Tq1rYwnC Emulation Platform dramatically reduces risk in the verification of today’s complex SoCs and is a core technology in the Mentor Enterprise Verification Platform™ (EVP).
Comprehensive verification support
Mentor’s software and application solutions and continual enhancements enable a comprehensive verification environment for IP, chip, and system level verification.
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Veloce Strato emulation platform consists of three main components: the chip, the operating system software and the hardware. Each main component delivers unique capabilities, but just as importantly, they are designed to work together to enhance user benefits and deliver exceptional verification productivity.
Veloce2 Emulator
The leading high-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs. The Veloce emulator accelerates block and full SoC RTL simulations during all phases of the design process.
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Veloce's innovative operating system, Veloce OS3, adds software programmability and resource management to the Veloce emulator. OS3 makes it easy to add new use models and extend the value of the platform.
Veloce VirtuaLAB
Veloce VirtuaLAB devices are software solutions that create a “virtual lab” environment for SoC verification. They provide greater flexibility and visibility over a target protocol in applications such as video/audio, storage, and networking as well as industry-standard bus protocols.
iSolve
iSolve solutions provide application and protocol-based solutions for several vertical market areas; including video/audio, networking, wireless, embedded software, and storage.
Veloce TestBench XPress
TestBench XPress (TBX) co-modeling software makes Veloce2 an ultrafast transaction-level modeling (TLM) verification engine, up to 10,000 times faster than software simulators, significantly reducing development schedule risks.
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Verification IP delivers higher levels of productivity for simulation and for acceleration of IP and SoC verification, easing the transition from simulation to acceleration.
Codelink
Codelink® establishes a highly productive, software-driven hardware debug environment with innovative features that make a debug session appear just like an interactive session while maintaining synchronization.
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Vista™ supports Electronic System Level (ESL) tool integration with Veloce2. An integrated TLM 2.0-based solution for architectural design exploration, verification, and virtual prototyping, it allows engineers to validate hardware and software early in the design cycle.
Other technologies
The Veloce platform also incorporates Mentor’s advanced functional verification methodology, to provide the same advanced capabilities as simulation for assertions, coverage, TLM, and UVM. In addition, Mentor JTAG solutions provide both physical and virtual JTAG connections to software development tools.
The Veloce Emulation Platform advantage
The Veloce emulation platform combines a unique hardware architecture, innovative operating system, specialized applications, and versatile peripheral solutions to deliver a comprehensive and flexible high-speed, high-capacity verification environment. Veloce accelerates simulation and provides uncompromised visibility and debug.
Its innovative Veloce operating system adds software programmability and resource management, making it easier to add new use models that extend the value of the emulator. The interplay of software innovation on powerful, flexible hardware makes emulation a more effective verification choice for more companies.
- State-of-the-art emulation SoC and scalable hardware configurations for verifying designs from 40 million to 15 billion gates.
- Acceleration of block, module, and full SoC regression test runs is many orders of magnitude faster than simulation
- Eliminates most silicon respins by running billions of cycles to find hard-to-find bugs missed by traditional methods
- Comprehensive and versatile simulation-like debug environment for ease-of-use
- Full system integration using real-world stimulus and software for testbenches before first silicon is available
- Simulation-like use model for assertion and coverage based verification
- Standard queuing support for optimal utilization of emulation resources among various teams and sites
- Veloce Apps leverage the proven, robust emulator capabilities to solve specific verification and validation challenges.